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ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
13 years 11 months ago
VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
Imran Ahmed, Tughrul Arslan
DSD
2010
IEEE
144views Hardware» more  DSD 2010»
13 years 7 months ago
On-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism
—Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated i...
Xiao Zhang, Hans G. Kerkhoff, Bart Vermeulen
TCS
2008
13 years 7 months ago
Role-based access control for boxed ambients
Our society is increasingly moving towards richer forms of information exchange where mobility of processes and devices plays a prominent role. This tendency has prompted the acad...
Adriana B. Compagnoni, Elsa L. Gunter, Philippe Bi...
SIES
2010
IEEE
13 years 5 months ago
Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks
In this paper we present an approach to increase the fault tolerance in FlexRay networks by introducing backup nodes to replace defect ECUs (Electronic Control Units). In order to ...
Kay Klobedanz, Gilles B. Defo, Wolfgang Mülle...
ET
2002
115views more  ET 2002»
13 years 7 months ago
CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing
As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CASBUS that solves ...
Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki