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ISVLSI
2007
IEEE
204views VLSI» more  ISVLSI 2007»
14 years 2 months ago
Designing Memory Subsystems Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance ...
Mahmoud Ben Naser, Yao Guo, Csaba Andras Moritz
GLVLSI
2007
IEEE
115views VLSI» more  GLVLSI 2007»
14 years 2 months ago
Novel architectures for efficient (m, n) parallel counters
Parallel counters are key elements in many arithmetic circuits, especially fast multipliers. In this paper, novel architectures and designs for high speed, low power (3, 2), (7, 3...
Sreehari Veeramachaneni, Lingamneni Avinash, Kirth...
ICCSA
2004
Springer
14 years 1 months ago
New Parameter for Balancing Two Independent Measures in Routing Path
The end-to-end characteristic is an important factor for QoS support. Since network users and their required bandwidths for applications increase, the efficient usage of networks h...
Moonseong Kim, Young-Cheol Bang, Hyunseung Choo
ICPP
2008
IEEE
14 years 2 months ago
Thermal Management for 3D Processors via Task Scheduling
A rising horizon in chip fabrication is the 3D integration technology. It stacks two or more dies vertically with a dense, high-speed interface to increase the device density and ...
Xiuyi Zhou, Yi Xu, Yu Du, Youtao Zhang, Jun Yang 0...
DATE
2010
IEEE
170views Hardware» more  DATE 2010»
14 years 1 months ago
Analytical model for TDDB-based performance degradation in combinational logic
With aggressive gate oxide scaling, latent defects in the gate oxide manifest as traps that, in time, lead to gate oxide breakdown. Progressive gate oxide breakdown, also referred...
Mihir Choudhury, Vikas Chandra, Kartik Mohanram, R...