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» Delay modelling improvement for low voltage applications
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ASPDAC
2007
ACM
120views Hardware» more  ASPDAC 2007»
13 years 12 months ago
Integrating Power Management into Distributed Real-time Systems at Very Low Implementation Cost
The development cost of low-power embedded systems can be significantly reduced by reusing legacy designs and applying proper modifications to meet the new power constraints. The ...
Bita Gorjiara, Nader Bagherzadeh, Pai H. Chou
ISLPED
2010
ACM
170views Hardware» more  ISLPED 2010»
13 years 8 months ago
Low-power sub-threshold design of secure physical unclonable functions
The unique and unpredictable nature of silicon enables the use of physical unclonable functions (PUFs) for chip identification and authentication. Since the function of PUFs depen...
Lang Lin, Daniel E. Holcomb, Dilip Kumar Krishnapp...
DAC
2009
ACM
14 years 9 months ago
Multicore parallel min-cost flow algorithm for CAD applications
Computational complexity has been the primary challenge of many VLSI CAD applications. The emerging multicore and manycore microprocessors have the potential to offer scalable perf...
Yinghai Lu, Hai Zhou, Li Shang, Xuan Zeng
TELETRAFFIC
2007
Springer
14 years 2 months ago
Is ALOHA Causing Power Law Delays?
Abstract. Renewed interest in ALOHA-based Medium Access Control (MAC) protocols stems from their proposed applications to wireless ad hoc and sensor networks that require distribut...
Predrag R. Jelenkovic, Jian Tan
ICCAD
2003
IEEE
113views Hardware» more  ICCAD 2003»
14 years 4 months ago
Retiming with Interconnect and Gate Delay
In this paper, we study the problem of retiming of sequential circuits with both interconnect and gate delay. Most retiming algorithms have assumed ideal conditions for the non-lo...
Chris C. N. Chu, Evangeline F. Y. Young, Dennis K....