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» Delay modelling improvement for low voltage applications
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WWW
2007
ACM
14 years 8 months ago
Delay tolerant applications for low bandwidth and intermittently connected users: the aAQUA experience
With the explosive growth and spread of Internet, web access from mobile and rural users has become significant. But these users face problems of low bandwidth and intermittent In...
Saurabh Sahni, Krithi Ramamritham
ISQED
2003
IEEE
303views Hardware» more  ISQED 2003»
14 years 1 months ago
Design and Analysis of Low-Voltage Current-Mode Logic Buffers
- This paper investigates important problems involved in the design of a CML buffer as well as a chain of tapered CML buffers. A new design procedure to systematically design a cha...
Payam Heydari
DATE
2007
IEEE
156views Hardware» more  DATE 2007»
14 years 2 months ago
Process variation tolerant low power DCT architecture
: 2-D Discrete Cosine Transform (DCT) is widely used as the core of digital image and video compression. In this paper, we present a novel DCT architecture that allows aggressive v...
Nilanjan Banerjee, Georgios Karakonstantis, Kaushi...
TVLSI
2002
104views more  TVLSI 2002»
13 years 7 months ago
A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops
This paper compares four previously published static dual-edge-triggered flip-flops (DETFFs) with a proposed design for their performance, power dissipation, and low-voltage low-po...
Wai Chung, Timothy Lo, Manoj Sachdev
DAC
2005
ACM
14 years 8 months ago
User-perceived latency driven voltage scaling for interactive applications
Power has become a critical concern for battery-driven computing systems, on which many applications that are run are interactive. System-level voltage scaling techniques, such as...
Le Yan, Lin Zhong, Niraj K. Jha