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» Delay-Insensitive Interface Specification and Synthesis
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FPL
2010
Springer
106views Hardware» more  FPL 2010»
13 years 6 months ago
Increasing Design Productivity through Core Reuse, Meta-data Encapsulation, and Synthesis
This paper presents a novel IP core reuse strategy which reduces design time from days to hours for communication circuits such as digital radio receivers. This design productivity...
Adam Arnesen, Kevin Ellsworth, Derrick Gibelyou, T...
ASYNC
2001
IEEE
164views Hardware» more  ASYNC 2001»
14 years 2 days ago
Synthesis and Implementation of a Signal-Type Asynchronous Data Communication Mechanism
This paper describes the synthesis and hardware implementation of a signal-type asynchronous data communication mechanism (ACM). Such an ACM can be used in systems where a data-dr...
Alexandre Yakovlev, Fei Xia, Delong Shang
ISSS
1999
IEEE
151views Hardware» more  ISSS 1999»
14 years 21 days ago
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...
Jens Horstmannshoff, Heinrich Meyr
SIGADA
2005
Springer
14 years 1 months ago
Using ASIS to generate C++ bindings
In this paper, we describe an approach to automatically creating C++ bindings to Ada libraries utilizing capabilities of the Ada Semantic Interface Specification (ASIS). We discus...
Howard Ausden, Karl A. Nyberg
ASE
2005
140views more  ASE 2005»
13 years 8 months ago
Automated Procedure Construction for Deductive Synthesis
Deductive program synthesis systems based on automated theorem proving offer the promise of software that is correct by construction. However, the difficulty encountered in constru...
Steve Roach, Jeffrey Van Baalen