86 search results - page 17 / 18 » Delay-Reduced Combinational Logic Synthesis using Multiplexe... |
ISLPED
2005
ACM
14 years 2 months ago
2005
ACM
This paper studies the impact on energy efficiency and thermal behavior of design style and clock-gating style in queue and array structures. These structures are major sources of...
FPL
2004
Springer
14 years 1 months ago
2004
Springer
Abstract. High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required ...
CODES
2008
IEEE
14 years 3 months ago
2008
IEEE
The combination of flit-buffer flow control methods and latency-insensitive protocols is an effective solution for networks-on-chip (NoC). Since they both rely on backpressure...
ATS
1998
IEEE
14 years 24 days ago
1998
IEEE
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
CAV
2008
Springer
13 years 10 months ago
2008
Springer
We present CSIsat, an interpolating decision procedure for the quantifier-free theory of rational linear arithmetic and equality with uninterpreted function symbols. Our implementa...