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ISCA
2006
IEEE
154views Hardware» more  ISCA 2006»
14 years 1 months ago
An Integrated Framework for Dependable and Revivable Architectures Using Multicore Processors
This paper presents a high-availability system architecture called INDRA — an INtegrated framework for Dependable and Revivable Architecture that enhances a multicore processor ...
Weidong Shi, Hsien-Hsin S. Lee, Laura Falk, Mrinmo...
HPCA
2009
IEEE
14 years 8 months ago
Bridging the computation gap between programmable processors and hardwired accelerators
New media and signal processing applications demand ever higher performance while operating within the tight power constraints of mobile devices. A range of hardware implementatio...
Kevin Fan, Manjunath Kudlur, Ganesh S. Dasika, Sco...
OOPSLA
2010
Springer
13 years 5 months ago
Hera-JVM: a runtime system for heterogeneous multi-core architectures
Heterogeneous multi-core processors, such as the IBM Cell processor, can deliver high performance. However, these processors are notoriously difficult to program: different cores...
Ross McIlroy, Joe Sventek
ICCAD
2006
IEEE
157views Hardware» more  ICCAD 2006»
14 years 4 months ago
From single core to multi-core: preparing for a new exponential
In the past, processor design trends were dominated by increasingly complex feature sets, higher clock speeds, growing thermal envelopes and increasing power dissipation. Recently...
Jeff Parkhurst, John A. Darringer, Bill Grundmann
IPPS
2007
IEEE
14 years 1 months ago
SWARM: A Parallel Programming Framework for Multicore Processors
Due to fundamental physical limitations and power constraints, we are witnessing a radical change in commodity microprocessor architectures to multicore designs. Continued perform...
David A. Bader, Varun Kanade, Kamesh Madduri