272 search results - page 53 / 55 » Dependability, power, and performance trade-off on a multico... |
CODES
2007
IEEE
14 years 2 months ago
2007
IEEE
This article presents a multiprocessor system-on-chip synthesis (MPSoC) algorithm that optimizes system mean time to failure. Given a set of directed acyclic periodic graphs of co...
TJS
2002
13 years 8 months ago
2002
A significant source for enhancing application performance and for reducing power consumption in embedded processor applications is to improve the usage of the memory hierarchy. In...
VLSISP
2008
13 years 8 months ago
2008
This paper describes a novel memory hierarchy and line-pixel-lookahead (LPL) for an H.264/AVC video decoder. The memory system is the bottleneck of most video processors, particula...
ECRTS
2007
IEEE
14 years 2 months ago
2007
IEEE
Of late, there has been a considerable interest in models, algorithms and methodologies specifically targeted towards designing hardware and software for streaming applications. ...
CODES
2009
IEEE
13 years 9 months ago
2009
IEEE
We present a novel loop transformation technique, particularly well suited for optimizing embedded compilers, where an increase in compilation time is acceptable in exchange for s...