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IPPS
2000
IEEE
14 years 27 days ago
Register Assignment for Software Pipelining with Partitioned Register Banks
Many techniques for increasing the amount of instruction-level parallelism (ILP) put increased pressure on the registers inside a CPU. These techniques allow for more operations t...
Jason Hiser, Steve Carr, Philip H. Sweany, Steven ...
SPAA
1999
ACM
14 years 24 days ago
Recursive Array Layouts and Fast Parallel Matrix Multiplication
Matrix multiplication is an important kernel in linear algebra algorithms, and the performance of both serial and parallel implementations is highly dependent on the memory system...
Siddhartha Chatterjee, Alvin R. Lebeck, Praveen K....
ICPPW
1999
IEEE
14 years 24 days ago
Improving Fairness and Privacy of Zhou-Gollmann's Fair Non-Repudiation Protocol
We deal with two claws of Zhou-Gollmann's fair nonrepudiation protocol. Firstly, their protocol divides a message into 2 parts, i.e., a key K and a ciphertext C. Then, C is d...
Kwangjo Kim, Sangjoon Park, Joonsang Baek
IEEEPACT
1999
IEEE
14 years 24 days ago
A Cost-Effective Clustered Architecture
In current superscalar processors, all floating-point resources are idle during the execution of integer programs. As previous works show, this problem can be alleviated if the fl...
Ramon Canal, Joan-Manuel Parcerisa, Antonio Gonz&a...
ICS
1999
Tsinghua U.
14 years 23 days ago
Low-level router design and its impact on supercomputer system performance
Supercomputer performance is highly dependent on its interconnection subsystem design. In this paper we study how di erent architectural approaches for router design impact into s...
Valentin Puente, José A. Gregorio, Cruz Izu...