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HIPEAC
2009
Springer
14 years 28 days ago
HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic
Abstract. Exposing more instruction-level parallelism in out-of-order superscalar processors requires increasing the number of dynamic in-flight instructions. However, large instru...
Suriya Subramanian, Kathryn S. McKinley
APSEC
2004
IEEE
14 years 24 days ago
Modeling the Impact of a Learning Phase on the Business Value of a Pair Programming Project
Pair programmers need a "warmup phase" before the pair can work at full speed. The length of the learning interval varies, depending on how experienced the developers are...
Frank Padberg, Matthias M. Müller
AUIC
2004
IEEE
14 years 24 days ago
Revisiting 2D vs 3D Implications on Spatial Memory
Prior research has shown that the efficient use of graphical user interfaces strongly depends on human capabilities for spatial cognition. Although it is tempting to believe that ...
Andy Cockburn
AUIC
2004
IEEE
14 years 24 days ago
Display and Presence Disparity in Mixed Presence Groupware
Mixed Presence Groupware (MPG) supports both colocated and distributed participants working over a shared visual workspace. It does this by connecting multiple single-display grou...
Anthony Tang, Michael Boyle, Saul Greenberg
CGO
2004
IEEE
14 years 24 days ago
FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths
Application-specific instruction set processors (ASIPs) have the potential to meet the challenging cost, performance, and power goals of future embedded processors by customizing ...
Manjunath Kudlur, Kevin Fan, Michael L. Chu, Rajiv...