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CC
2004
Springer
14 years 1 months ago
Using Multiple Memory Access Instructions for Reducing Code Size
An important issue in embedded systems design is the size of programs. As computing devices decrease in size, yet with more and more functions, better code size optimizations are i...
Neil Johnson, Alan Mycroft
FPGA
2004
ACM
126views FPGA» more  FPGA 2004»
14 years 1 months ago
A synthesis oriented omniscient manual editor
The cost functions used to evaluate logic synthesis transformations for FPGAs are far removed from the final speed and routability determined after placement, routing and timing a...
Tomasz S. Czajkowski, Jonathan Rose
IESS
2007
Springer
162views Hardware» more  IESS 2007»
14 years 1 months ago
Automatic Parallelization of Sequential Specifications for Symmetric MPSoCs
Abstract This paper presents an embedded system design toolchain for automatic generation of parallel code runnable on symmetric multiprocessor systems from an initial sequential s...
Fabrizio Ferrandi, Luca Fossati, Marco Lattuada, G...
EUROSYS
2008
ACM
13 years 9 months ago
Efficient guaranteed disk request scheduling with fahrrad
Guaranteed I/O performance is needed for a variety of applications ranging from real-time data collection to desktop multimedia to large-scale scientific simulations. Reservations...
Anna Povzner, Tim Kaldewey, Scott A. Brandt, Richa...
ICCAD
2009
IEEE
119views Hardware» more  ICCAD 2009»
13 years 5 months ago
Iterative layering: Optimizing arithmetic circuits by structuring the information flow
Current logic synthesis techniques are ineffective for arithmetic circuits. They perform poorly for XOR-dominated circuits, and those with a high fan-in dependency between inputs ...
Ajay K. Verma, Philip Brisk, Paolo Ienne