Timing closure problems occur when timing estimates computed during logic synthesis do not match with timing estimates computed from the layout of the circuit. In such a situation...
Wilsin Gosti, Sunil P. Khatri, Alberto L. Sangiova...
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
We introduce an Information Extraction (IE) system which uses the logical theory of an ontology as a generalisation of the typical information extraction patterns to extract biolog...
Little work has been completed which addresses the logical composition and use of ternary relationships in entity-relationship modeling. Many modeling notations and most CASE tool...
We propose the notion of rewriting modules in order to provide a structural and hierarchical approach of TRS. We define then relative dependency pairs built upon these modules whic...