Sciweavers

19 search results - page 2 / 4
» Depth optimal incremental mapping for field programmable gat...
Sort
View
FPGA
2001
ACM
145views FPGA» more  FPGA 2001»
13 years 12 months ago
Simultaneous logic decomposition with technology mapping in FPGA designs
Conventional technology mapping algorithms for SRAM-based Field Programmable Gate Arrays (FPGAs) are normally carried out on a fixed logic decomposition of a circuit. The impact o...
Gang Chen, Jason Cong
DATE
2010
IEEE
134views Hardware» more  DATE 2010»
13 years 6 months ago
Combining optimizations in automated low power design
—Starting from sequential programs, we present an approach combining data reuse, multi-level MapReduce, and pipelining to automatically find the most power-efficient designs th...
Qiang Liu, Tim Todman, Wayne Luk
ICVS
2001
Springer
13 years 12 months ago
Compiling SA-C Programs to FPGAs: Performance Results
Abstract. At the first ICVS, we presented SA-C (“sassy”), a singleassignment variant of the C programming language designed to exploit both coarse-grain and fine-grain parallel...
Bruce A. Draper, A. P. Wim Böhm, Jeffrey Hamm...
ASAP
2011
IEEE
233views Hardware» more  ASAP 2011»
12 years 7 months ago
Accelerating vision and navigation applications on a customizable platform
—The domain of vision and navigation often includes applications for feature tracking as well as simultaneous localization and mapping (SLAM). As these problems require computati...
Jason Cong, Beayna Grigorian, Glenn Reinman, Marco...
TCSV
2008
120views more  TCSV 2008»
13 years 7 months ago
A Parallel Hardware Architecture for Scale and Rotation Invariant Feature Detection
Abstract--This paper proposes a parallel hardware architecture for image feature detection based on the SIFT (Scale Invariant Feature Transform) algorithm and applied to the SLAM (...
Vanderlei Bonato, Eduardo Marques, George A. Const...