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BIRTHDAY
2005
Springer
14 years 28 days ago
Synthesis Revisited: Generating Statechart Models from Scenario-Based Requirements
Constructing a program from a specification is a long-known general and fundamental problem. Besides its theoretical interest, this question also has practical implications, since...
David Harel, Hillel Kugler, Amir Pnueli
INDIASE
2009
ACM
14 years 1 days ago
Automated review of natural language requirements documents: generating useful warnings with user-extensible glossaries driving
We present an approach to automating some of the quality assurance review of software requirements documents, and promoting best practices for requirements documentation. The syst...
Prateek Jain, Kunal Verma, Alex Kass, Reymonrod G....
FDL
2007
IEEE
14 years 1 months ago
Automatic High Level Assertion Generation and Synthesis for Embedded System Design
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
Lun Li, Frank P. Coyle, Mitchell A. Thornton
VL
2005
IEEE
14 years 29 days ago
Transformation of UML State Machines for Direct Execution
Executable UML models are nowadays gaining interest in embedded systems design. This domain is strongly devoted to the modeling of reactive behavior using StateChart variants. In ...
Tim Schattkowsky, Wolfgang Müller 0003
ASSETS
2007
ACM
13 years 11 months ago
Evaluating American Sign Language generation through the participation of native ASL signers
We discuss important factors in the design of evaluation studies for systems that generate animations of American Sign Language (ASL) sentences. In particular, we outline how some...
Matt Huenerfauth, Liming Zhao, Erdan Gu, Jan M. Al...