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138
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DATE
2005
IEEE
154views Hardware» more  DATE 2005»
15 years 8 months ago
A Time Slice Based Scheduler Model for System Level Design
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...
Luciano Lavagno, Claudio Passerone, Vishal Shah, Y...
97
Voted
ISCAS
2008
IEEE
119views Hardware» more  ISCAS 2008»
15 years 9 months ago
Adjusting the neurons models in neuromimetic ICs using the voltage-clamp technique
— This paper presents an original method to tune a neuromimetic IC based on neuron conductance-based models (Hodgkin-Huxley formalism). This method is well known in electrophysio...
Sylvain Saïghi, Laure Buhry, Yannick Bornat, ...
129
Voted
OOPSLA
2004
Springer
15 years 8 months ago
Method-level phase behavior in java workloads
Java workloads are becoming more and more prominent on various computing devices. Understanding the behavior of a Java workload which includes the interaction between the applicat...
Andy Georges, Dries Buytaert, Lieven Eeckhout, Koe...
138
Voted
SCP
2008
128views more  SCP 2008»
15 years 2 months ago
Mobile JikesRVM: A framework to support transparent Java thread migration
Today's complex applications must face the distribution of data and code among different network nodes. Computation in distributed contexts is demanding increasingly powerful...
Raffaele Quitadamo, Giacomo Cabri, Letizia Leonard...
ISSS
2000
IEEE
91views Hardware» more  ISSS 2000»
15 years 7 months ago
Instruction-based System-level Power Evaluation of System-On-A-Chip Peripheral Cores
Various system-level core-based power evaluation approaches for core types like microprocessors, caches, main memories, and buses, have been proposed in the past. Approaches for o...
Tony Givargis, Frank Vahid, Jörg Henkel