Sciweavers

751 search results - page 61 / 151
» Design, Implementation, and Evaluation of Optimizations in a...
Sort
View
LCTRTS
2007
Springer
14 years 2 months ago
Tetris: a new register pressure control technique for VLIW processors
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
Weifeng Xu, Russell Tessier
CODES
2004
IEEE
13 years 11 months ago
Operation tables for scheduling in the presence of incomplete bypassing
Register bypassing is a powerful and widely used feature in modern processors to eliminate certain data hazards. Although complete bypassing is ideal for performance, bypassing ha...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
CSCLP
2008
Springer
13 years 9 months ago
From Rules to Constraint Programs with the Rules2CP Modelling Language
In this paper, we present a rule-based modelling language for constraint programming, called Rules2CP. Unlike other modelling languages, Rules2CP adopts a single knowledge represen...
François Fages, Julien Martin
ANCS
2011
ACM
12 years 7 months ago
ReClick - A Modular Dataplane Design Framework for FPGA-Based Network Virtualization
Network virtualization has emerged as a powerful technique to deploy novel services and experimental protocols over shared network infrastructures. Although recent research has hi...
Deepak Unnikrishnan, Justin Lu, Lixin Gao, Russell...
DATE
2005
IEEE
154views Hardware» more  DATE 2005»
14 years 1 months ago
A Time Slice Based Scheduler Model for System Level Design
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...
Luciano Lavagno, Claudio Passerone, Vishal Shah, Y...