135 search results - page 12 / 27 » Design, layout and verification of an FPGA using automated t... |
ACMSE
2005
ACM
14 years 1 months ago
2005
ACM
Through the automation of empirical evaluation we hope to alleviate evaluation problems encountered by software designers who are relatively new to the process. Barriers to good e...
TACAS
1998
Springer
13 years 12 months ago
1998
Springer
A state/event model is a concurrent version of Mealy machines used for describing embedded reactive systems. This paper introduces a technique that uses compositionality and depend...
ITC
2003
IEEE
14 years 29 days ago
2003
IEEE
Functional verification of complex designs largely relies on the use of simulation in conjunction high-level verification languages (HVL) and test-bench automation (TBA) tools. In...
TSMC
2010
13 years 2 months ago
2010
Computer system reliability is conventionally modeled and analyzed using techniques such as fault tree analysis (FTA) and reliability block diagrams (RBD), which provide static rep...
MSE
2003
IEEE
14 years 29 days ago
2003
IEEE
A tool has been created for use in a design course to automate integration of new components into a SystemOn-Chip (SoC). Students used this tool to implement a complete SoC Intern...