135 search results - page 4 / 27 » Design, layout and verification of an FPGA using automated t... |
DAC
2005
ACM
14 years 8 months ago
2005
ACM
We describe IODINE, a tool to automatically extract likely design properties using dynamic analysis. A practical bottleneck in the formal verification of hardware designs is the n...
AAAI
1994
13 years 9 months ago
1994
1 User interface design and development for knowledgebased systems and most other types of applications is a resource-consuming activity. Thus, many attempts have been made to auto...
IJCAI
2003
13 years 9 months ago
2003
Automated verification is one of the most success ful applications of automated reasoning in com puter science. In automated verification one uses algorithmic techniques to es...
VLSID
2003
IEEE
14 years 8 months ago
2003
IEEE
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
FPGA
2000
ACM
13 years 11 months ago
2000
ACM
In this paper we present a "high-level" FPGA architecture description language which lets FPGA architects succinctly and quickly describe an FPGA routing architecture. W...