3130 search results - page 47 / 626 » Design Correctness of Digital Systems |
DSD
2008
IEEE
14 years 2 months ago
2008
IEEE
In this paper, we examine the digital hardware design and implementation of a novel compact block cipher, referred to as PUFFIN, that is suitable for embedded applications. An imp...
ASPDAC
2010
ACM
13 years 5 months ago
2010
ACM
Modern digital IC designs have a critical operating point, or "wall of slack", that limits voltage scaling. Even with an errortolerance mechanism, scaling voltage below a...
CDC
2009
IEEE
14 years 11 days ago
2009
IEEE
— In this paper we propose an approach to control design of nonlinear time–delay systems, which is based on the construction of symbolic models, where each symbolic state and e...
AHS
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper, we propose a design methodology for implementing a multimode (or multi-configuration) and multi-throughput system into a single hardware architecture. The inputs of...
DSD
2008
IEEE
14 years 2 months ago
2008
IEEE
In this paper, a methodology for generating VHDL descriptions of hardware checkers is presented. It is shown how the methodology can be used to generate on-line checkers of commun...