Sciweavers

59 search results - page 3 / 12
» Design Error Diagnosis in Digital Circuits without Error Mod...
Sort
View
DAC
2000
ACM
14 years 8 months ago
Self-test methodology for at-speed test of crosstalk in chip interconnects
The effect of crosstalk errors is most significant in highperformance circuits, mandating at-speed testing for crosstalk defects. This paper describes a self-test methodology that...
Xiaoliang Bai, Sujit Dey, Janusz Rajski
ISCAS
2007
IEEE
106views Hardware» more  ISCAS 2007»
14 years 1 months ago
Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design
—Two probabilistic-based models, namely the Ensemble-Dependent Matrix model [1][3] and the Markov Random Field model [2], have been proposed to deal with faults in nanoscale syst...
Huifei Rao, Jie Chen, Changhong Yu, Woon Tiong Ang...
WCE
2007
13 years 8 months ago
Circuit Noise Interference on Sampling Clock and Its Effect on A/D Conversion
—Clock jitter and its effects on signal-to-noise ratio (SNR) were widely investigated in the published literatures. However, most of the issues mainly focused on white-Gaussian-n...
Sun Lei, An Jianping, Wu Yanbo
ISQED
2007
IEEE
125views Hardware» more  ISQED 2007»
14 years 1 months ago
Modeling of PMOS NBTI Effect Considering Temperature Variation
Negative bias temperature instability (NBTI) has come to the forefront of critical reliability phenomena in advanced CMOS technology. In this paper, we propose a fast and accurate...
Hong Luo, Yu Wang 0002, Ku He, Rong Luo, Huazhong ...
FMCAD
2007
Springer
13 years 11 months ago
Circuit Level Verification of a High-Speed Toggle
As VLSI fabrication technology progresses to 65nm feature sizes and smaller, transistors no longer operate as ideal switches. This motivates verifying digital circuits using contin...
Chao Yan, Mark R. Greenstreet