123 search results - page 10 / 25 » Design For Testability Method for CML Digital Circuits |
ICCD
2000
IEEE
14 years 4 months ago
2000
IEEE
This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating of the ground bounce is presen...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
A digital combinational logic circuit is reversible if it maps each input pattern to a unique output pattern. Such circuits are of interest in quantum computing, optical computing...
ICCAD
2007
IEEE
14 years 4 months ago
2007
IEEE
— We introduce a remote activation scheme that aims to protect integrated circuits (IC) intellectual property (IP) against piracy. Remote activation enables designers to lock eac...
JUCS
2007
13 years 7 months ago
2007
: It is a difficult problem that using cellular neural network to make up of analog signal processing circuit. This paper presented the architecture of new cellular neural network ...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardeni...