123 search results - page 13 / 25 » Design For Testability Method for CML Digital Circuits |
ICCAD
1993
IEEE
13 years 11 months ago
1993
IEEE
Circuit simulation is one of the most computationally expensive tasks in circuit design and optimization. Detailed simulation at the level of precision of SPICE is usually perform...
DAC
1994
ACM
13 years 11 months ago
1994
ACM
Asynchronous circuits are crucial in designing low power and high performance digital systems. In this paper, we present an ecient modular partitioning approach for asynchronous c...
ISCAS
2007
IEEE
14 years 2 months ago
2007
IEEE
— Low-power consumption has become a highly important concern for synchronous standard-cell design, and consequently mandates the use of low-power design methodologies and techni...
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
DSD
2002
IEEE
14 years 19 days ago
2002
IEEE
We use a formal tool to extract Finite State Machines (FSM) based representations (lists of states and transitions) of sequential circuits described by flip-flops and gates. The...