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» Design For Testability Method for CML Digital Circuits
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DELTA
2006
IEEE
14 years 1 months ago
Minimizing Simultaneous Switching Noise (SSN) using Modified Odd/Even Bus Invert Method
In high speed digital circuits, the inductive effect is more dominant compared to capacitive effect. In particular, as the technology is shrinking, the spacing between interconnec...
K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srini...
KES
2008
Springer
13 years 7 months ago
Incremental evolution of a signal classification hardware architecture for prosthetic hand control
Evolvable Hardware (EHW) is a new method for designing electronic circuits. However, there are several problems to solve for making high performance systems. One is the limited sca...
Jim Torresen
ASPDAC
2004
ACM
169views Hardware» more  ASPDAC 2004»
14 years 1 months ago
Design of real-time VGA 3-D image sensor using mixed-signal techniques
— We have developed the first real-time 3-D image sensor with VGA pixel resolution using mixed-signal techniques to achieve high-speed and high-accuracy range calculation based ...
Yusuke Oike, Makoto Ikeda, Kunihiro Asada
FPL
2008
Springer
154views Hardware» more  FPL 2008»
13 years 9 months ago
Numerical function generators using bilinear interpolation
Two-variable numerical functions are widely used in various applications, such as computer graphics and digital signal processing. Fast and compact hardware implementations are re...
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
ICC
2007
IEEE
115views Communications» more  ICC 2007»
13 years 11 months ago
Super-Wideband SSN Suppression in High-Speed Digital Communication Systems by Using Multi-Via Electromagnetic Bandgap Structures
With the advance of semiconductor manufacturing, There are many approaches to deal with these problems. EDA, and VLSI design technologies, circuits with even higher Adding discrete...
MuShui Zhang, YuShan Li, LiPing Li, Chen Jia