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» Design For Testability Method for CML Digital Circuits
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ICES
2000
Springer
140views Hardware» more  ICES 2000»
13 years 11 months ago
Evolving Cellular Automata for Self-Testing Hardware
Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-In Self-Test) techniques is increasingly popular, but requires efficient algori...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
SLIP
2005
ACM
14 years 1 months ago
Congestion prediction in early stages
Routability optimization has become a major concern in the physical design cycle of VLSI circuits. Due to the recent advances in VLSI technology, interconnect has become a dominan...
Chiu-Wing Sham, Evangeline F. Y. Young
DAC
2007
ACM
14 years 8 months ago
Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting
The number and magnitude of process variation sources are increasing as we scale further into the nano regime. Today's most successful response surface methods limit us to lo...
Amith Singhee, Rob A. Rutenbar
DAC
2004
ACM
14 years 8 months ago
Large-scale full-wave simulation
We describe a new extraction tool, EMX (Electro-Magnetic eXtractor), for the analysis of RF, analog and high-speed digital circuits. EMX is a fast full-wave field solver. It incor...
Sharad Kapur, David E. Long
SENSYS
2004
ACM
14 years 1 months ago
Hardware design experiences in ZebraNet
The enormous potential for wireless sensor networks to make a positive impact on our society has spawned a great deal of research on the topic, and this research is now producing ...
Pei Zhang, Christopher M. Sadler, Stephen A. Lyon,...