59 search results - page 11 / 12 » Design Framework for Partial Run-Time FPGA Reconfiguration |
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
Modern digital signal processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many appl...
ERSA
2010
13 years 5 months ago
2010
In this paper, we introduce the open-source PivPav backend tool for reconfigurable computing. Essentially, PivPav provides an interface to a library of digital circuits that are ke...
DATE
2008
IEEE
2008
IEEE
An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications
14 years 1 months ago
Novel reconfigurable computing platforms enable efficient realizations of complex signal processing applications by allowing exploitation of parallelization resulting in high thro...
FCCM
2011
IEEE
12 years 10 months ago
2011
IEEE
— Recent progress in High-Level Synthesis (HLS) es has helped raise the abstraction level of FPGA programming. However implementation and performance evaluation of the HLS-genera...
ICALP
2010
Springer
13 years 11 months ago
2010
Springer
Abstract. We provide a framework for the design and analysis of dynamic programming algorithms for surface-embedded graphs on n vertices and branchwidth at most k. Our technique ap...