Design flow for embedded FPGAs based on a flexible architecture template

Modern digital signal processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many applications, the growth of algorithmic complexity is already faster than the growth of computational power provided by discrete general purpose processors [1]. A typical approach to address this problem is the combination of a processor core with dedicated accelerators. Since changes in standards or algorithms can change the demands on the accelerators, an attractive alternative to highly customised VLSImacros is the use of reconfigurable embedded FPGAs (eFPGAs). First commercial products combining a general purpose processor core and an embedded FPGA recently emerged (e.g. Stretch S6000 [2], Menta eFPGAaugmented CPUs [3]). For many digital signal processing applications, a significantly improved efficiency in terms of power dissipation, throughput and chip area can be achieved by tailoring both the processor co...

• Type: Conference
• Year: 2008
• Where: DATE
• Authors: B. Neumann, Thorsten von Sydow, Holger Blume, Tobias G. Noll
• Keywords: DATE 2008, Digital Signal Processing, Hardware, Processor Core, Signal Processing Applications