Sciweavers

59 search results - page 6 / 12
» Design Framework for Partial Run-Time FPGA Reconfiguration
Sort
View
FPGA
2004
ACM
137views FPGA» more  FPGA 2004»
14 years 1 months ago
Making visible the thermal behaviour of embedded microprocessors on FPGAs: a progress report
This paper shows a method to verifying the thermal status of complex FPGA-based circuits like microprocessors. Thus, the designer can evaluate if a particular block is working bey...
Sergio López-Buedo, Eduardo I. Boemo
ASAP
2008
IEEE
167views Hardware» more  ASAP 2008»
14 years 2 months ago
Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms
Process technology has reduced in size such that it is possible to implement complete applicationspecific architectures as Systems-on-Chip (SoCs) using both Application-Specific I...
David Dickin, Lesley Shannon
ERSA
2007
174views Hardware» more  ERSA 2007»
13 years 9 months ago
High-Level Specification of Runtime Reconfigurable Designs
”C to Gates” compilers for FPGAs have been a topic of investigation for nearly two decades. Some of these endeavors have reached a point of viability. Impulse C, for example, ...
Stephen D. Craven, Peter M. Athanas
JCP
2007
154views more  JCP 2007»
13 years 7 months ago
Partially Reconfigurable Vector Processor for Embedded Applications
—Embedded systems normally involve a combination of hardware and software resources designed to perform dedicated tasks. Such systems have widely crept into industrial control, a...
Muhammad Z. Hasan, Sotirios G. Ziavras
VLSID
2009
IEEE
142views VLSI» more  VLSID 2009»
14 years 8 months ago
Floorplanning for Partial Reconfiguration in FPGAs
Partial Reconfiguration on heterogeneous Field Programmable Gate Arrays (FPGA) with millions of gates yields better utilization of resources by swapping in and out the active modu...
Pritha Banerjee, Megha Sangtani, Susmita Sur-Kolay