434 search results - page 11 / 87 » Design Methodologies and Architecture Solutions for High-Per... |
ISVLSI
2002
IEEE
14 years 18 days ago
2002
IEEE
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
Directed test program-based verification or formal verification methods are usually quite ineffective on large cachecoherent, non-uniform memory access (CC-NUMA) multiprocessors b...
VLSI
2007
Springer
14 years 1 months ago
2007
Springer
— In the future, high performance computing systems may consist of multiple multicore processors and reconfigurable logic coprocessors. Industry trends indicate that such coproc...
DAC
1997
ACM
13 years 12 months ago
1997
ACM
This paper describes a new design methodology to analyze the on-chip power supply noise for high performance microprocessors. Based on an integrated package-level and chip-level p...
ISCA
2008
IEEE
14 years 2 months ago
2008
IEEE
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...