Sciweavers

434 search results - page 33 / 87
» Design Methodologies and Architecture Solutions for High-Per...
Sort
View
EIT
2009
IEEE
14 years 2 months ago
System-level memory modeling for bus-based memory architecture exploration
—System-level design (SLD) provides a solution to the challenge of increasing design complexity and time-to-market pressure in modern embedded system designs. In this paper, we p...
Zhongbo Cao, Ramon Mercado, Diane T. Rover
CODES
2005
IEEE
14 years 1 months ago
Designing real-time H.264 decoders with dataflow architectures
High performance microprocessors are designed with generalpurpose applications in mind. When it comes to embedded applications, these architectures typically perform controlintens...
Youngsoo Kim, Suleyman Sair
ISLPED
2005
ACM
85views Hardware» more  ISLPED 2005»
14 years 1 months ago
A low-power crossroad switch architecture and its core placement for network-on-chip
As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the...
Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
SOSP
1993
ACM
13 years 9 months ago
The Information Bus - An Architecture for Extensible Distributed Systems
Research can rarely be performed on large-scale, distributed systems at the level of thousands of workstations. In this paper, we describe the motivating constraints, design princ...
Brian M. Oki, Manfred Pflügl, Alex Siegel, Da...
CF
2007
ACM
13 years 11 months ago
Reconfigurable hybrid interconnection for static and dynamic scientific applications
As we enter the era of petascale computing, system architects must plan for machines composed of tens or even hundreds of thousands of processors. Although fully connected network...
Shoaib Kamil, Ali Pinar, Daniel Gunter, Michael Li...