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ICPPW
2002
IEEE
14 years 20 days ago
A Statistical Approach for the Analysis of the Relation Between Low-Level Performance Information, the Code, and the Environment
This paper presents a methodology for aiding a scientific programmer to evaluate the performance of parallel programs on advanced architectures. It applies well-defined design o...
Nayda G. Santiago, Diane T. Rover, Domingo Rodr&ia...
DAC
2008
ACM
14 years 8 months ago
An integrated nonlinear placement framework with congestion and porosity aware buffer planning
Due to skewed scaling of interconnect delay and cell delay with technology scaling, modern VLSI timing closure requires use of extensive buffer insertion. Inserting a large number...
Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pa...
MJ
2006
145views more  MJ 2006»
13 years 7 months ago
A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems
In this paper, we propose a method for speeding-up Digital Signal Processing applications by partitioning them between the reconfigurable hardware blocks of different granularity ...
Michalis D. Galanis, Athanasios Milidonis, Athanas...
ASPDAC
2005
ACM
132views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Automatic synthesis and scheduling of multirate DSP algorithms
- To date, most high-level synthesis systems do not automatically solve present design problems, such as those related to timing associated with the physical implementation of mult...
Ying Yi, Mark Milward, Sami Khawam, Ioannis Nousia...
ISCA
2012
IEEE
302views Hardware» more  ISCA 2012»
11 years 10 months ago
Scale-out processors
The emergence of global-scale online services has galvanized scale-out software, characterized by splitting vast datasets and massive computation across many independent servers. ...
Pejman Lotfi-Kamran, Boris Grot, Michael Ferdman, ...