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SIGCOMM
2004
ACM
14 years 1 months ago
Work-conserving distributed schedulers for Terabit routers
−Buffered multistage interconnection networks offer one of the most scalable and cost-effective approaches to building high capacity routers. Unfortunately, the performance of su...
Prashanth Pappu, Jonathan S. Turner, Kenneth Wong
P2P
2002
IEEE
14 years 19 days ago
Multishelf: An Experiment in Peer-to-Peer Infomediation
This paper describes the architecture and the implementation of Multishelf - a decentralized Peerto-Peer infomediator. Multishelf was designed and built during a ten-week senior s...
Zary Segall, Andrew Fortier, Gerd Kortuem, Jay Sch...
DATE
2000
IEEE
140views Hardware» more  DATE 2000»
14 years 3 days ago
Resolution of Dynamic Memory Allocation and Pointers for the Behavioral Synthesis from C
-- One of the greatest challenges in C/C++-based design methodology is to efficiently map C/C++ models into hardware. Many of the networking and multimedia applications implemente...
Luc Séméria, Koichi Sato, Giovanni D...
ISCA
2012
IEEE
320views Hardware» more  ISCA 2012»
11 years 10 months ago
Viper: Virtual pipelines for enhanced reliability
The reliability of future processors is threatened by decreasing transistor robustness. Current architectures focus on delivering high performance at low cost; lifetime device rel...
Andrea Pellegrini, Joseph L. Greathouse, Valeria B...
DSD
2010
IEEE
221views Hardware» more  DSD 2010»
13 years 5 months ago
Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis
Reconfigurable FPGA based Systems-on-Chip (SoC) architectures are increasingly becoming the preferred solution for implementing modern embedded systems, due to their flexible natur...
Sana Cherif, Imran Rafiq Quadri, Samy Meftali, Jea...