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» Design Patterns for Reconfigurable Computing
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IPPS
2006
IEEE
14 years 1 months ago
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...
DAC
2007
ACM
14 years 8 months ago
Novel CNTFET-based Reconfigurable Logic Gate Design
This paper describes a family of novel dynamically reconfigurable logic gates based on double-gate carbon nanotube field-effect transistors which demonstrate p-type or n-type switc...
David Navarro, Frédéric Gaffiot, Ian...
DATE
2003
IEEE
123views Hardware» more  DATE 2003»
14 years 23 days ago
Parallel Processing Architectures for Reconfigurable Systems
Novel reconfigurable computing architectures exploit the inherent parallelism available in many signalprocessing problems. These architectures often consist of networks of compute...
Kees A. Vissers
APCSAC
2001
IEEE
13 years 11 months ago
The First Real Operating System for Reconfigurable Computers
Traditional reconfigurable computing platforms are designed to be single user and have been acknowledged to be difficult to design applications for. The design tools are still pri...
Grant B. Wigley, David A. Kearney