Sciweavers

1734 search results - page 75 / 347
» Design Patterns for Reconfigurable Computing
Sort
View
DAC
2009
ACM
16 years 3 months ago
A DVS-based pipelined reconfigurable instruction memory
Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the instruction cache consumes a significant fraction of the ...
Zhiguo Ge, Tulika Mitra, Weng-Fai Wong
105
Voted
FPL
2006
Springer
124views Hardware» more  FPL 2006»
15 years 5 months ago
A Dynamically Reconfigurable Queue Scheduler
In this paper we present the design and implementation of a dynamically reconfigurable system for packet queue scheduling. Two widely accepted queue schedulers have been implement...
Christoforos Kachris, Stamatis Vassiliadis
101
Voted
ASPDAC
2001
ACM
120views Hardware» more  ASPDAC 2001»
15 years 5 months ago
Virtual Java/FPGA interface for networked reconfiguration
Abstract- Avirtual interfacebetweenJava andFPGA for networked reconfigurationis presented. ThroughtheJavaflFPGAinterface,Java applicationscan exploithardwareaccelerators with FPGAs...
Yajun Ha, Geert Vanmeerbeeck, Patrick Schaumont, S...
CDES
2006
184views Hardware» more  CDES 2006»
15 years 3 months ago
Compilation for Future Nanocomputer Architectures
Compilation has a long history of translating a programmer's human-readable code into machine instructions designed to make good use of a specific target computer. In this pa...
Thomas P. Way
IPPS
2006
IEEE
15 years 8 months ago
Automatic application-specific microarchitecture reconfiguration
Applications for constrained embedded systems are subject to strict time constraints and restrictive resource utilization. With soft core processors, application developers can cu...
Shobana Padmanabhan, Ron K. Cytron, Roger D. Chamb...