605 search results - page 13 / 121 » Design Principles for Combiners with Memory |
ISCA
1996
IEEE
14 years 23 days ago
1996
IEEE
Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to addres...
ICCAD
2007
IEEE
14 years 5 months ago
2007
IEEE
An algorithm for technology mapping of combinational and sequential logic networks is proposed and applied to mapping into K-input lookup-tables (K-LUTs). The new algorithm avoids...
ASAP
2004
IEEE
14 years 11 days ago
2004
IEEE
Distributed local memories, or scratchpads, have been shown to effectively reduce cost and power consumption of application-specific accelerators while maintaining performance. Th...
VLSID
2007
IEEE
14 years 9 months ago
2007
IEEE
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
HIS
2008
13 years 10 months ago
2008
This paper addresses the application of a PCA analysis on categorical data prior to diagnose a patients data set using a Case-Based Reasoning (CBR) system. The particularity is th...