605 search results - page 72 / 121 » Design Principles for Combiners with Memory |
ISNN
2005
Springer
14 years 2 months ago
2005
Springer
Built on the theories of biological neural network, artificial neural network methods have shown many significant advantages. However, the memory space in an artificial neural chip...
RT
2004
Springer
14 years 2 months ago
2004
Springer
We introduce a tiled 3D MIP map representation of global illumination data. The representation is an adaptive, sparse octree with a “brick” at each octree node; each brick con...
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
Novel reconfigurable computing architectures exploit the inherent parallelism available in many signalprocessing problems. These architectures often consist of networks of compute...
ICPP
1999
IEEE
14 years 1 months ago
1999
IEEE
This paper describes the challenges presented by singlechip parallel media processors (PMPs). These machines integrate multiple parallel function units, instruction execution, and...
FPGA
2006
ACM
14 years 11 days ago
2006
ACM
This paper presents experimental measurements of the differences between a 90nm CMOS FPGA and 90nm CMOS Standard Cell ASICs in terms of logic density, circuit speed and power cons...