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» Design Recovery of a Two Level System
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ACSC
2003
IEEE
14 years 29 days ago
Communication Performance Issues for Two Cluster Computers
Clusters of commodity machines have become a popular way of building cheap high performance parallel computers. Many of these designs rely on standard Ethernet networks as a syste...
Francis Vaughan, Duncan A. Grove, Paul D. Coddingt...
IRI
2007
IEEE
14 years 1 months ago
Reuse Technique in Hardware Design
The paper presents a technique for the design of digital systems on the basis of reusable hardware templates, which are circuits with modifiable functionality that might be custom...
Valery Sklyarov, Iouliia Skliarova
DATE
2005
IEEE
132views Hardware» more  DATE 2005»
14 years 1 months ago
Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage
In this paper, we investigate the impact of Tox and Vth on power performance trade-offs for on-chip caches. We start by examining the optimization of the various components of a s...
Robert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylve...
DATE
2006
IEEE
147views Hardware» more  DATE 2006»
14 years 1 months ago
Quantitative analysis of transaction level models for the AMBA bus
The increasing complexity of embedded systems pushes system designers to higher levels of abstraction. Transaction Level Modeling (TLM) has been proposed to model ation in systems...
Gunar Schirner, Rainer Dömer
RSP
1999
IEEE
160views Control Systems» more  RSP 1999»
13 years 12 months ago
Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping
SDL is currently gaining interest as a system level specification language for HW/SW codesign. Automated synthesis of SDL in hardware so far had problems with its efficiency. The ...
Oliver Bringmann, Wolfgang Rosenstiel, Annette Mut...