50 search results - page 3 / 10 » Design Rewiring Using ATPG |
ITC
1997
IEEE
13 years 11 months ago
1997
IEEE
As the sizes of general and special purpose processors increase rapidly, generating high quality manufacturing tests for them is becoming a serious problem in industry. This paper...
DDECS
2006
IEEE
14 years 1 months ago
2006
IEEE
- Extension of a BIST design algorithm is proposed in this paper. The method is based on a synthesis of a combinational block - the decoder, transforming pseudo-random code words i...
IOLTS
2008
IEEE
14 years 1 months ago
2008
IEEE
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient err...
ATS
2009
IEEE
14 years 1 months ago
2009
IEEE
High performance designs often use the on-chip device PLLs for accurate test clock generation during testing. The on-chip clock generator is designed in a programmable way to faci...
VTS
2007
IEEE
14 years 1 months ago
2007
IEEE
The sensitivity of very deep submicron designs to supply voltage noise is increasing due to higher path delay variations and reduced noise margins with supply noise scaling. The s...