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ISVLSI
2008
IEEE
173views VLSI» more  ISVLSI 2008»
15 years 10 months ago
System Level Design Space Exploration for Multiprocessor System on Chip
Future embedded systems will integrate hundreds of processors. Current design space exploration methods cannot cope with such a complexity. It is mandatory to extend these methods...
Issam Maalej, Guy Gogniat, Jean Luc Philippe, Moha...
JSA
2010
173views more  JSA 2010»
14 years 11 months ago
Hardware/software support for adaptive work-stealing in on-chip multiprocessor
During the past few years, embedded digital systems have been requested to provide a huge amount of processing power and functionality. A very likely foreseeable step to pursue th...
Quentin L. Meunier, Frédéric P&eacut...
DATE
2006
IEEE
102views Hardware» more  DATE 2006»
15 years 10 months ago
Faster exploration of high level design alternatives using UML for better partitions
Partitioning is a time consuming and computationally complex optimization problem in the codesign of hardware software systems. The stringent time-to-market requirements have resu...
Waseem Ahmed, Doug Myers
CODES
2006
IEEE
15 years 10 months ago
The pipeline decomposition tree: : an analysis tool for multiprocessor implementation of image processing applications
Modern embedded systems for image processing involve increasingly complex levels of functionality under real-time and resourcerelated constraints. As this complexity increases, th...
Dong-Ik Ko, Shuvra S. Bhattacharyya
CODES
2006
IEEE
15 years 10 months ago
TLM/network design space exploration for networked embedded systems
This paper presents a methodology to combine Transaction Level Modeling and System/Network co-simulation for the design of networked embedded systems. As a result, a new design di...
Nicola Bombieri, Franco Fummi, Davide Quaglia