79 search results - page 6 / 16 » Design Space Exploration for Massively Parallel Processor Ar... |
HICSS
1997
IEEE
14 years 16 hour ago
1997
IEEE
The SB-PRAM is a massively parallel, uniform memory access (UMA) shared memory computer. The main ideas of the design are multithreading on instruction level, hashing of the addre...
DELTA
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper describes the concept, architecture, development and demonstration of a real time, high performance, software defined 4-receiver system and a space time decoder to be i...
ISCAS
2003
IEEE
14 years 1 months ago
2003
IEEE
A new vision chip, SCAMP-2, has been developed in a 0.35µm CMOS technology. In this paper, the design of the chip is presented, with particular emphasis on its readout architectu...
DAMON
2007
Springer
14 years 2 months ago
2007
Springer
Recently, graphics processing units, or GPUs, have become a viable alternative as commodity, parallel hardware for generalpurpose computing, due to their massive data-parallelism,...
ARC
2008
Springer
13 years 9 months ago
2008
Springer
Abstract. In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications....