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ISCA
2010
IEEE
219views Hardware» more  ISCA 2010»
14 years 22 days ago
Using hardware vulnerability factors to enhance AVF analysis
Fault tolerance is now a primary design constraint for all major microprocessors. One step in determining a processor’s compliance to its failure rate target is measuring the Ar...
Vilas Sridharan, David R. Kaeli
APSEC
2005
IEEE
14 years 1 months ago
Exception Handling: An Architecture Model and Utility Support
Exception handling design is an important but difficult subject in software development. In Java software development, the use of checked exceptions exacerbates the difficulty. In...
Yu Chin Cheng, Jung-Sing Jwo
PRDC
1999
IEEE
13 years 12 months ago
An Architecture-Based Software Reliability Model
In this paper we present an analytical model for estimating architecture-based software reliability, according to the reliability of each component, the operational profile, and t...
Wen-Li Wang, Ye Wu, Mei-Hwa Chen
HASE
2007
IEEE
14 years 2 months ago
Integrating Product-Line Fault Tree Analysis into AADL Models
Fault Tree Analysis (FTA) is a safety-analysis technique that has been recently extended to accommodate product-line engineering for critical domains. This paper describes a tool-...
Hongyu Sun, Miriam Hauptman, Robyn R. Lutz
MICRO
2009
IEEE
124views Hardware» more  MICRO 2009»
14 years 2 months ago
ZerehCache: armoring cache architectures in high defect density technologies
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...