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» Design and Analysis of Fault Tolerant Architectures by Model...
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IEEECIT
2010
IEEE
13 years 6 months ago
CFCSS without Aliasing for SPARC Architecture
With the increasing popularity of COTS (commercial off the shelf) components and multi-core processor in space and aviation applications, software fault tolerance becomes attracti...
Chao Wang, Zhongchuan Fu, Hongsong Chen, Wei Ba, B...
DAC
2006
ACM
14 years 8 months ago
Unknown-tolerance analysis and test-quality control for test response compaction using space compactors
For a space compactor, degradation of fault detection capability caused by the masking effects from unknown values is much more serious than that caused by error masking (i.e. ali...
Mango Chia-Tso Chao, Kwang-Ting Cheng, Seongmoon W...
ISCA
2007
IEEE
130views Hardware» more  ISCA 2007»
14 years 1 months ago
Dynamic prediction of architectural vulnerability from microarchitectural state
Transient faults due to particle strikes are a key challenge in microprocessor design. Driven by exponentially increasing transistor counts, per-chip faults are a growing burden. ...
Kristen R. Walcott, Greg Humphreys, Sudhanva Gurum...
SIGMOD
2010
ACM
377views Database» more  SIGMOD 2010»
14 years 14 days ago
Online aggregation and continuous query support in MapReduce
MapReduce is a popular framework for data-intensive distributed computing of batch jobs. To simplify fault tolerance, the output of each MapReduce task and job is materialized to ...
Tyson Condie, Neil Conway, Peter Alvaro, Joseph M....
DAC
2009
ACM
14 years 8 months ago
Fault models for embedded-DRAM macros
In this paper, we compare embedded-DRAM (eDRAM) testing to both SRAM testing and commodity-DRAM testing, since an eDRAM macro uses DRAM cells with an SRAM interface. We first star...
Ching-Yu Chin, Hao-Yu Yang, Mango Chia-Tso Chao, R...