665 search results - page 28 / 133 » Design and Analysis of a Dynamically Reconfigurable Network ... |
ASAP
2007
IEEE
14 years 1 months ago
2007
IEEE
We present a design of a customized crossbar scheduler for on-chip networks. The proposed scheduler arbitrates on-demand interconnects, where physical topologies are identical to ...
ICMCS
2005
IEEE
14 years 2 months ago
2005
IEEE
The software codec on mobile device introduces significant power consumption because the energy efficiency of general processor based system is much lower than that of the dedicat...
ASPLOS
2004
ACM
14 years 2 months ago
2004
ACM
Multiple Clock Domain (MCD) processors are a promising future alternative to today’s fully synchronous designs. Dynamic Voltage and Frequency Scaling (DVFS) in an MCD processor ...
DSD
2010
IEEE
13 years 9 months ago
2010
IEEE
—Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated i...
PPOPP
2006
ACM
14 years 3 months ago
2006
ACM
IP forwarding is one of the main bottlenecks in Internet backbone routers, as it requires performing the longest-prefix match at 10Gbps speed or higher. IPv6 forwarding further ex...