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DAC
2010
ACM
13 years 10 months ago
Network on chip design and optimization using specialized influence models
In this study, we propose the use of specialized influence models to capture the dynamic behavior of a Network-onChip (NoC). Our goal is to construct a versatile modeling framewor...
Cristinel Ababei
DSN
2005
IEEE
13 years 11 months ago
SoftArch: An Architecture Level Tool for Modeling and Analyzing Soft Errors
Soft errors are a growing concern for processor reliability. Recent work has motivated architecture-level studies of soft errors since the architecture can mask many raw errors an...
Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. ...
TC
2008
13 years 9 months ago
Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
INFOCOM
2009
IEEE
14 years 3 months ago
VISA: Virtual Scanning Algorithm for Dynamic Protection of Road Networks
—This paper proposes a VIrtual Scanning Algorithm (VISA), tailored and optimized for road network surveillance. Our design uniquely leverages upon the facts that (i) the movement...
Jaehoon Jeong, Yu Gu, Tian He, David Du
SIGCOMM
2009
ACM
14 years 3 months ago
A programmable, generic forwarding element approach for dynamic network functionality
Communication networks are growing exponentially, and new services and applications are being introduced unceasingly. To meet the demands of these services and applications, curre...
Ran Giladi, Niv Yemini