Sciweavers

761 search results - page 143 / 153
» Design and Analysis of a Robust Pipelined Memory System
Sort
View
MICRO
2008
IEEE
138views Hardware» more  MICRO 2008»
14 years 1 months ago
Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs
As the number of transistors integrated on a chip continues to increase, a growing challenge is accurately modeling performance in the early stages of processor design. Analytical...
Xi E. Chen, Tor M. Aamodt
IEEEPACT
2005
IEEE
14 years 1 months ago
HUNTing the Overlap
Hiding communication latency is an important optimization for parallel programs. Programmers or compilers achieve this by using non-blocking communication primitives and overlappi...
Costin Iancu, Parry Husbands, Paul Hargrove
ACSAC
2002
IEEE
14 years 15 days ago
A Practical Approach to Identifying Storage and Timing Channels: Twenty Years Later
Secure computer systems use both mandatory and discretionary access controls to restrict the flow of information through legitimate communication channels such as files, shared ...
Richard A. Kemmerer
EUROGP
2009
Springer
105views Optimization» more  EUROGP 2009»
14 years 5 days ago
Quantum Circuit Synthesis with Adaptive Parameters Control
The contribution presented herein proposes an adaptive genetic algorithm applied to quantum logic circuit synthesis that, dynamically adjusts its control parameters. The adaptation...
Cristian Ruican, Mihai Udrescu, Lucian Prodan, Mir...
SASN
2006
ACM
14 years 1 months ago
Attack-resilient hierarchical data aggregation in sensor networks
In a large sensor network, in-network data aggregation, i.e., combining partial results at intermediate nodes during message routing, significantly reduces the amount of communic...
Sankardas Roy, Sanjeev Setia, Sushil Jajodia