761 search results - page 27 / 153 » Design and Analysis of a Robust Pipelined Memory System |
DAC
2000
ACM
14 years 8 months ago
2000
ACM
Latency insensitive design has been recently proposed in literature as a way to design complex digital systems, whose functional behavior is robust with respect to arbitrary varia...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Abstract— Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield...
FPL
1995
Springer
13 years 11 months ago
1995
Springer
Although the energy required to perform a logic operation has continuously dropped at least by ten orders of magnitude since early vacuumtube electronics [1], the increasing clock ...
CODES
2008
IEEE
14 years 2 months ago
2008
IEEE
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
ICRA
2003
IEEE
14 years 27 days ago
2003
IEEE
In this paper the control of exible joint manipulators is studied in detail. A composite control algorithm is proposed for the exible joint robots, which consists of two main part...