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» Design and Analysis of a Robust Pipelined Memory System
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ASAP
2006
IEEE
130views Hardware» more  ASAP 2006»
14 years 1 months ago
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip
Data-Pipelining is a widely used model to represent streaming applications. Incremental decomposition and optimization of a data-pipelining application onto a multi-processor plat...
Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, ...
RTAS
2008
IEEE
14 years 1 months ago
Hybrid Timing Analysis of Modern Processor Pipelines via Hardware/Software Interactions
Embedded systems are often subject to constraints that require determinism to ensure that task deadlines are met. Such systems are referred to as real-time systems. Schedulability...
Sibin Mohan, Frank Mueller
CODES
2006
IEEE
14 years 1 months ago
The pipeline decomposition tree: : an analysis tool for multiprocessor implementation of image processing applications
Modern embedded systems for image processing involve increasingly complex levels of functionality under real-time and resourcerelated constraints. As this complexity increases, th...
Dong-Ik Ko, Shuvra S. Bhattacharyya
SIGSOFT
2003
ACM
14 years 8 months ago
ARCHER: using symbolic, path-sensitive analysis to detect memory access errors
Memory corruption errors lead to non-deterministic, elusive crashes. This paper describes ARCHER (ARray CHeckER) a static, effective memory access checker. ARCHER uses path-sensit...
Yichen Xie, Andy Chou, Dawson R. Engler
MICRO
1999
IEEE
98views Hardware» more  MICRO 1999»
13 years 11 months ago
Access Region Locality for High-Bandwidth Processor Memory System Design
This paper studies an interesting yet less explored behavior of memory access instructions, called access region locality. Unlike the traditional temporal and spatial data localit...
Sangyeun Cho, Pen-Chung Yew, Gyungho Lee