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ICCD
2007
IEEE
132views Hardware» more  ICCD 2007»
14 years 5 months ago
Post-layout comparison of high performance 64b static adders in energy-delay space
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...
Sheng Sun, Carl Sechen
PDP
2010
IEEE
14 years 3 months ago
Impact of Parallel Workloads on NoC Architecture Design
— Due to the multi-core processors, the importance of parallel workloads has increased considerably. However, manycore chips demand new interconnection strategies, since traditio...
Henrique Cota de Freitas, Lucas Mello Schnorr, Mar...
MICRO
2007
IEEE
167views Hardware» more  MICRO 2007»
14 years 2 months ago
Informed Microarchitecture Design Space Exploration Using Workload Dynamics
Program runtime characteristics exhibit significant variation. As microprocessor architectures become more complex, their efficiency depends on the capability of adapting with wor...
Chang-Burm Cho, Wangyuan Zhang, Tao Li
IWQOS
2004
Springer
14 years 1 months ago
Yaksha: a self-tuning controller for managing the performance of 3-tiered Web sites
— Managing the performance of multiple-tiered Web sites under high client loads is a critical problem with the advent of dynamic content and database-driven servers on the Intern...
Abhinav Kamra, Vishal Misra, Erich M. Nahum
CCGRID
2010
IEEE
13 years 7 months ago
An Adaptive Data Prefetcher for High-Performance Processors
—While computing speed continues increasing rapidly, data-access technology is lagging behind. Data-access delay, not the processor speed, becomes the leading performance bottlen...
Yong Chen, Huaiyu Zhu, Xian-He Sun