455 search results - page 5 / 91 » Design and Evaluation of a High Performance Dynamically Exte... |
PDP
2007
IEEE
14 years 2 months ago
2007
IEEE
—Grid computing is becoming more and more attractive for coordinating large-scale heterogeneous resource sharing and problem solving. Of particular interest for effective Grid co...
RTSS
2006
IEEE
14 years 2 months ago
2006
IEEE
In this paper, we describe the design and evaluation of a scheduler (referred to as Everest) for allocating processors to services in high performance, multi-service routers. A sc...
ISCA
2008
IEEE
14 years 3 months ago
2008
IEEE
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
DAC
2000
ACM
14 years 28 days ago
2000
ACM
– This paper describes the system design and implementation of Active Basestations, a novel application of the run-time reconfigurable hardware technology whose applications have...
MICRO
2009
IEEE
14 years 3 months ago
2009
IEEE
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for mult...