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HPCA
2008
IEEE
16 years 3 months ago
Regional congestion awareness for load balance in networks-on-chip
Interconnection networks-on-chip (NOCs) are rapidly replacing other forms of interconnect in chip multiprocessors and system-on-chip designs. Existing interconnection networks use...
Paul Gratz, Boris Grot, Stephen W. Keckler
110
Voted
CGO
2010
IEEE
15 years 8 months ago
Contention aware execution: online contention detection and response
Cross-core application interference due to contention for shared on-chip and off-chip resources pose a significant challenge to providing application level quality of service (Qo...
Jason Mars, Neil Vachharajani, Robert Hundt, Mary ...
131
Voted
IPPS
2007
IEEE
15 years 9 months ago
Exploring a Multithreaded Methodology to Implement a Network Communication Protocol on the Cyclops-64 Multithreaded Architecture
The IBM Cyclops-64 (C64) chip employs a multithreaded architecture that integrates a large number of hardware thread units on a single chip. A cellular supercomputer is being deve...
Ge Gan, Ziang Hu, Juan del Cuvillo, Guang R. Gao
SEUS
2008
IEEE
15 years 9 months ago
Delay-Aware Mobile Transactions
In the expanding e-society, mobile embedded systems are increasingly used to support transactions such as for banking, stock or database applications. Such systems entail a range o...
Brahim Ayari, Abdelmajid Khelil, Neeraj Suri
114
Voted
ASAP
2007
IEEE
134views Hardware» more  ASAP 2007»
15 years 5 months ago
Methodology and Toolset for ASIP Design and Development Targeting Cryptography-Based Applications
Network processors utilizing general-purpose instruction-set architectures (ISA) limit network throughput due to latency incurred from cryptography and hashing applications (AES, ...
David Montgomery, Ali Akoglu