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» Design and Implementation of Power-Aware Virtual Memory
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ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
13 years 9 months ago
Translation caching: skip, don't walk (the page table)
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
Thomas W. Barr, Alan L. Cox, Scott Rixner
EMSOFT
2008
Springer
13 years 9 months ago
Tax-and-spend: democratic scheduling for real-time garbage collection
Real-time Garbage Collection (RTGC) has recently advanced to the point where it is being used in production for financial trading, military command-and-control, and telecommunicat...
Joshua S. Auerbach, David F. Bacon, Perry Cheng, D...
FPL
2006
Springer
156views Hardware» more  FPL 2006»
13 years 11 months ago
Improving Usability of FPGA-Based Reconfigurable Computers Through Operating System Support
Advances in FPGA-based reconfigurable computers have made them a viable computing platform for a vast variety of computation demanding areas such as bioinformatics, speech recogni...
Hayden Kwok-Hay So, Robert W. Brodersen
IJCNN
2008
IEEE
14 years 1 months ago
Hybrid learning architecture for unobtrusive infrared tracking support
—The system architecture presented in this paper is designed for helping an aged person to live longer independently in their own home by detecting unusual and potentially hazard...
K. K. Kiran Bhagat, Stefan Wermter, Kevin Burn
ANCS
2007
ACM
13 years 11 months ago
Optimal packet scheduling in output-buffered optical switches with limited-range wavelength conversion
All-optical packet switching is a promising candidate for future high-speed switching. However, due to the absence of optical Random Access Memory, the traditional Virtual Output ...
Lin Liu, Yuanyuan Yang